Efficient FPGA Based Bidirectional Network on Chip Router throgh Virtual Channel Regulator

Ashish Khodwe Ashish Khodwe

Abstract


Fundamental unit of building a Network on Chip
is the router; it directs the packets according to a routing
algorithm to the desired host. Both NoC performance and
energy budget depend heavily on the routers' buffer
resources. This paper introduces a novel Bidirectional
Network on chip router with unified buffer structure, called
the dynamic Virtual Channel Regulator, which dynamically
allocates Virtual Channels (VC) and buffer resources
according to network traffic conditions. In this study, we
analyse the move towards Networks-on-Chips router from
an area and power perspective by accurately modeling a
Bidirectional Network-on-chip router through Virtual
Channel Regulator in FPGA. Accurate speed, area and
power metrics are also reported for the networks router,
which will allow a more complete comparison to be made
across the NoC architectural router space considered. The
proposed architecture of BiNoC router is simulated in Xilinx
ISE 9.1i software. We designed a router with scalability
feature which is synthesized in models of Virtex-II XC2VP30
FPGA infrastructures. The source code is written in VHDL.
In addition, the proposed router uses low resource utilization
percentage of FPGA. From the implementation results, the
proposed router is operated with higher speed, area in terms
of slices reduced by 38.55% and the LUTs reduced by
44.59%

Keywords


Interconnection networks, on-chip communication, Reconfigurable, NoC, FPGA

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